1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits. In particular, the present invention relates to the art of placing cells on semiconductor chips with controlled wire congestion.
2. Description of Related Art
An integrated circuit chip (hereafter referred to as an "IC" or a "chip") comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins which must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins to be connected. A netlist is a list of nets for a chip.
FIG. 1 shows a common organization of an IC. On a semiconductor substrate 10, vertical strips of alternating columns 12 and channels 14 are defined. The cells 16 are fabricated in the columns, and the channels are typically used for running vertical wires to connect the pins 18 of the cells 16. For illustrative purposes, only the rectilinear connections as illustrated by the wire 20. Therefore, all distances are measured using rectilinear or Manhattan distance.
For simplicity, the chip 8 of FIG. 1 shows only a few columns; however, in a practical implementation, it is common for a chip to have many hundreds of columns and channels, and hundreds of thousands of cells and about the same number of nets.
The channels of a chip are commonly used to run vertical wires for the chip. To run horizontal wires, another layer of material is fabricated on the surface of the chip. Via's are used to bring the pins up to the second layer for the horizontal connections. If the surface area is at premium, yet another, third layer of material may be fabricated on top of the horizontal-wire layer. This third layer may be used to run the vertical wires, and the width of the channels may be reduced to decrease the overall surface area requirement.
Because there are a large number of pins to connect and the complex nature of the connections required, a proper placement of the cells and the routing of the wires are critical for a successful implementation of a chip. Some placement and routing schemes may result in uneven distribution of cells and wires leading to congestion in some areas of the chip while other areas of the chip may be sparsely used. If the congestion is such that the number of wires required to connect the nets for a particular area is greater than the maximum number of wires which can be fabricated on that region, then that placement cannot be implemented.